Blog 11: Finishing up Year 1 and looking forward

Hiya,

the past weeks have, again, been quite busy and stressful, but I managed at least;)

We have finished the Processor Design Project course, although we haven’t received a grade yet, so it’s to be decided if we are done after all;) The deadline of the report/design was last Monday (June 13th), so that Sunday we spent the whole afternoon and night on finishing up our design and to make our report. Unfortunately, we were not able to implement the 2-way associative cache. It seems that the memory structure that was implemented was optimized for Direct Mapped, so if we are to get the 2-way associative cache to work, we should look at the memory structure as well (instead of just looking at how the entries are stored). Luckily we achieved other improvements: bigger cache and better DDR to cache mapping and a Radix-4 multiplier and divider that need 16 instead of 32 cycles to get the result. The overall result is an increase in performance of almost 62.5% with negligible power increase (0.001 W); the area increase is significant unfortunately. Increasing block size (instead of retrieving 32 bits from the DDR at once we retrieve 64 bits) seemed to work except on one benchmark. The results of our improved processor in comparison with the baseline are shown below. 2 days after the deadline we had a symposium in which we showed our design and the results. The conclusion we took home was that we should have done a proper benchmark analysis. If we had done that, we probably wouldn’t have tried (and failed;)) to implement a branch predictor.

Improved processor vs baseline on needed execution cycles, area and power usage (Click for a better view; note: Y-axis is performance, meaning 1.x is better and 0.x is worse)

Improved processor vs baseline on needed execution cycles, area and power usage (Click for a better view; note: Y-axis is performance, meaning 1.x is better and 0.x is worse)

After PDP (temporarily) finished, I’ve been focusing on Quantum. Before this, however, I finished labs 3, 4 and 5. Labs 4 and 5 went pretty well, so I expect good grades;) As I was saying, last week till today I have been focusing on the Final Lab of this course (there is no exam). It consisted of 5 assignments (related to quantum circuits), of which assignment 3 was the hardest. Last week I finished all assignments except 3; it took me quite some time however. The assignments were definitely harder than the previous 2 labs, however this only meant I had to spend more time on them. I’m pretty sure I did quite well on these 4. One assignment was working on the Ninja Star circuit which can be seen below.

Example of a Surface Code circuit. If there is no error (0 instead of 1 for example) in any of the data qubits (D1-D9), no ancilla qubit (X/Z1-X/Z4). But let's say there is a bit-flip error in D3. This means that ancilla Z3 fires and becomes 1 (Z ancilla's fire when there is a X/bit-flip error).

Example of a Surface Code circuit. If there is no error (0 instead of 1 for example) in any of the data qubits (D1-D9), no ancilla qubit (X/Z1-X/Z4) will fire. But let’s say there is a bit-flip error in D3. This means that ancilla Z2 fires and becomes 1 (Z ancilla’s fire when there is a X/bit-flip error).


The 3rd assignment was about Grover’s algorithm, which is quite ingenious. It would take me some time to explain it, so instead I give you a link for the interested people;) I will say this, however: this algorithm is a good example of why Quantum Computing shows promise.

System Engineering:( Last Friday the symposium was held. I have to admit that it was pretty interesting to see what the other groups have worked on (2 minute pitch per group only;)) and to look at other groups’ posters. We also had to defend our own poster, which wasn’t that bad. Anyway, the course is finished now:) All that is left is to wait for the grade, hopefully I will get it soon!

So what’s next? Coming Tuesday is my (voluntary!) retake for Computer Arithmetic; let’s see if I can improve my grade. I only got a 6 on the exam, while I got a 8.something on the take home exam. I will also have to start on the VLSI SoC project with my partner. Probably we will do that next week after the retake. Somewhere these 2 weeks I will also meet with my internship supervisor, so that he can sign my application form. Then I can hand in this application form and just wait for approval:)

Oh, I forgot one thing. The past weeks I’ve also been talking with Dr. R. van Leuken of the Circuits and Systems group (CAS) here at the TU. He signed my Individual Exam Programme (basically your list of courses), so I will most likely (99%) do my Master Thesis with him as supervisor, next year when I get back from my internship in Germany. I advice you all to arrange these things a little bit earlier;) It takes more time than you image to arrange an internship and your Master Thesis:(

One more thing: Holiday:) I got my visa without further problems, so next Friday (July 1st) I will embark on the plane to China:D I’m thrilled to go; I’m less thrilled to pack:P Most likely I will also work on VLSI SoC in China and work on my Chinese, but the main focus will be holiday;)

I’m not sure when my next blog will be, it might be somewhere in the holidays, otherwise it will be when I get back (either from China or internship). I hope you at least enjoyed my blogs a bit, but most of all that they were helpful. Hell, maybe I convinced some of you to join me next year in CE 🙂

That’s it for me for now. Good luck finishing this school year, and have an amazing holiday. Hope to see some of you in Delft next year:P

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