Blog 7: Getting back my life and start of Q3

Hi y’all,

the last 3 weeks have been the hardest ones of this year. Most of it, I have been finishing up on the project (two times extended deadline) while at the same time following lectures.

Let me first get Digital IC Design over with. If I think back to it, I’m still amazed we managed to finish it. Two weeks ago, in the final week before the deadline, we still had quite some stuff to do. Combining all the pieces didn’t take so much time, but sizing all the transistors, to get exact timing results took a lot more time than anticipated. Needless to say, we were happy with the week extension that was announced one(!) day before the initial deadline. At this point, all we had for the report was an introduction, so yeah. Anyway, after this joyful news, we took it a bit more relaxed for two days before going back to hardcore IC design. We oversaw many small things, which resulted in us (mainly my colleague though) having to size the transistors over and over again, which might not be hard, but it takes a lot of time and is so tedious. Moreover, we didn’t know that each component needed a pin for Vdd and Ground, so I spent a lot of time altering all the components of our system. At this point we are already in the last week, and it’s quite clear to us that there will be no time for the layout. Up untill the day before the deadline, we are trying to get our TDC to work with the provided testbench; this was (un)surprisingly harder than expected. We finally got it to work, and were planning to spend the last day on simulations and the report. And then: another extension untill the Monday. At this point, we just wanted it to be finished, we already put so much time on this project:( When we left Friday (later than 8 pm!) something still didn’t work completely. My colleague fixed it over the weekend, and Monday we ran simulations and wrote the report. On Tuesday, we showed the working of our design to the TAs, who told us that not many groups showed their designs up untill then. The TAs were pretty lenient and they saw our 5 ps resolution (yay:D).

Eventhough we have spent so much time on the project, and that we had countless of days where we stayed till 8 pm, I do not regret taking this course. I have learned a lot, and at times the project was actually fun:) I do think that the project was a bit too complicated, and that not everything was communicated clearly (Vdd pins anyone:P?). I also think that, because we were still working on this project 3 weeks into Q3, the project messes with the courses of Q3, which is not preferable. Next Monday and Tuesday there will be symposiums in which every group will present their TDC design. My presentation will be Tuesday, however I need to be there Monday as well. I’ll let you know how it went:)

Three weeks have already passed of quarter 3:O This quarter, I have decided to follow Computer Arithmetic (Track course), VLSI Test Technology and Reliability and Network Security (Specialization courses). I actually wanted to take Operating Systems as homologation (bachelor) course, but the exam conflicted with my compulsory common core course System Engineering. Jup, 4 courses again this quarter:P

System Engineering is about multi-discplinary design of systems. It is about high-level design and integration of blocks, of which you don’t necessarily need to know the complete functioning. I have two lectures (both starting 8:45:(); on Thursday a guest lecture is given that shows the place of System Engineering in the industry and on Friday a theory lecture is given in which the steps in System Engineering will be explained. This will be needed for next quarter; then we will work in groups of 11 students from different programs. In this project, we will have to design a system following some steps of System Engineering. Frankly, I don’t like the Thursday lectures, and I’m not thrilled for the project; the Friday lectures are okay. At the end of this quarter I will have an exam based on (mostly) the Friday lectures.

VLSI TT&R is about the testing of a chip. Did you know that functional testing of an 129 input and 65 output adder takes 2.15 x 10^22 years (source: Prof. S. Hamdioui)? Well, neither did I;) This course is all about making chips testable; how can chips be tested in a fast way, without costing too much while catching all the bad chips? Besides the theory, links are made with the industry. It’s a really interesting course, and so far I’m glad I took it. Prof. Hamdioui is very enthusiastic too, which helps a lot in liking the course:P There is no written exam for this course. There are three labs (groups of three), which consists of first applying the theory to test circuits and secondly of applying the theory on test circuits in software. At the end of this quarter there will be an oral exam, in which three students will have to design a test for a given circuit.

Network Security is quite an interesting course as well. The professor will, over the course of this quarter, go over all layers of the OSI model (including things as Wifi and tapping ethernet cables) and will show us why all consisting protocols are unsafe. He also requested us to send him encrypted (pgp) emails:P So far, the course has been quite intensive, but as I said quite interesting as well. There will be no written exam for this course. During the quarter, exercise sheets will be given that will account for 35% of the grade. Besides that, an essay (or a software/hardware project) has to written. The topic I have gotten is methods of Threat Analysis (such as Attack Trees, see below). I have started already, and almost finished the first (Attack Trees) out of three methods.

Famous Attack Tree example of Schneier. The top node is the goal of the attacker; the nodes below that are actions to achieve the goal. Source: https://www.schneier.com/images/paper-attacktrees-fig5.gif

There is not much to say about Computer Arithmetic yet honestly. Until now it has just been following lectures and practicing with a homework assignment. These assignments are optional and will be explained in class. There will be practice take-home exam, which will be graded. After that, in the exam week there is a written exam which will be similar to the take-home exam. So far, the course has been quite intensive.

Such a long blog haha. I guess that’s it for now (felt good to rant about IC design:P). Oh one more thing; yesterday I had a shadow day. This means that a student joined me for my classes. That was my first time; think it went well:) If you think CE is something for you, but you are not sure, feel free to sign-up for a shadow day:)

Well, that’s it! Till next blog:)

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