Posted in February 2016

Blog 7: Getting back my life and start of Q3

Hi y’all,

the last 3 weeks have been the hardest ones of this year. Most of it, I have been finishing up on the project (two times extended deadline) while at the same time following lectures.

Let me first get Digital IC Design over with. If I think back to it, I’m still amazed we managed to finish it. Two weeks ago, in the final week before the deadline, we still had quite some stuff to do. Combining all the pieces didn’t take so much time, but sizing all the transistors, to get exact timing results took a lot more time than anticipated. Needless to say, we were happy with the week extension that was announced one(!) day before the initial deadline. At this point, all we had for the report was an introduction, so yeah. Anyway, after this joyful news, we took it a bit more relaxed for two days before going back to hardcore IC design. We oversaw many small things, which resulted in us (mainly my colleague though) having to size the transistors over and over again, which might not be hard, but it takes a lot of time and is so tedious. Moreover, we didn’t know that each component needed a pin for Vdd and Ground, so I spent a lot of time altering all the components of our system. At this point we are already in the last week, and it’s quite clear to us that there will be no time for the layout. Up untill the day before the deadline, we are trying to get our TDC to work with the provided testbench; this was (un)surprisingly harder than expected. We finally got it to work, and were planning to spend the last day on simulations and the report. And then: another extension untill the Monday. At this point, we just wanted it to be finished, we already put so much time on this project:( When we left Friday (later than 8 pm!) something still didn’t work completely. My colleague fixed it over the weekend, and Monday we ran simulations and wrote the report. On Tuesday, we showed the working of our design to the TAs, who told us that not many groups showed their designs up untill then. The TAs were pretty lenient and they saw our 5 ps resolution (yay:D).

Eventhough we have spent so much time on the project, and that we had countless of days where we stayed till 8 pm, I do not regret taking this course. I have learned a lot, and at times the project was actually fun:) I do think that the project was a bit too complicated, and that not everything was communicated clearly (Vdd pins anyone:P?). I also think that, because we were still working on this project 3 weeks into Q3, the project messes with the courses of Q3, which is not preferable. Next Monday and Tuesday there will be symposiums in which every group will present their TDC design. My presentation will be Tuesday, however I need to be there Monday as well. I’ll let you know how it went:)

Three weeks have already passed of quarter 3:O This quarter, I have decided to follow Computer Arithmetic (Track course), VLSI Test Technology and Reliability and Network Security (Specialization courses). I actually wanted to take Operating Systems as homologation (bachelor) course, but the exam conflicted with my compulsory common core course System Engineering. Jup, 4 courses again this quarter:P

System Engineering is about multi-discplinary design of systems. It is about high-level design and integration of blocks, of which you don’t necessarily need to know the complete functioning. I have two lectures (both starting 8:45:(); on Thursday a guest lecture is given that shows the place of System Engineering in the industry and on Friday a theory lecture is given in which the steps in System Engineering will be explained. This will be needed for next quarter; then we will work in groups of 11 students from different programs. In this project, we will have to design a system following some steps of System Engineering. Frankly, I don’t like the Thursday lectures, and I’m not thrilled for the project; the Friday lectures are okay. At the end of this quarter I will have an exam based on (mostly) the Friday lectures.

VLSI TT&R is about the testing of a chip. Did you know that functional testing of an 129 input and 65 output adder takes 2.15 x 10^22 years (source: Prof. S. Hamdioui)? Well, neither did I;) This course is all about making chips testable; how can chips be tested in a fast way, without costing too much while catching all the bad chips? Besides the theory, links are made with the industry. It’s a really interesting course, and so far I’m glad I took it. Prof. Hamdioui is very enthusiastic too, which helps a lot in liking the course:P There is no written exam for this course. There are three labs (groups of three), which consists of first applying the theory to test circuits and secondly of applying the theory on test circuits in software. At the end of this quarter there will be an oral exam, in which three students will have to design a test for a given circuit.

Network Security is quite an interesting course as well. The professor will, over the course of this quarter, go over all layers of the OSI model (including things as Wifi and tapping ethernet cables) and will show us why all consisting protocols are unsafe. He also requested us to send him encrypted (pgp) emails:P So far, the course has been quite intensive, but as I said quite interesting as well. There will be no written exam for this course. During the quarter, exercise sheets will be given that will account for 35% of the grade. Besides that, an essay (or a software/hardware project) has to written. The topic I have gotten is methods of Threat Analysis (such as Attack Trees, see below). I have started already, and almost finished the first (Attack Trees) out of three methods.

Famous Attack Tree example of Schneier. The top node is the goal of the attacker; the nodes below that are actions to achieve the goal. Source: https://www.schneier.com/images/paper-attacktrees-fig5.gif

There is not much to say about Computer Arithmetic yet honestly. Until now it has just been following lectures and practicing with a homework assignment. These assignments are optional and will be explained in class. There will be practice take-home exam, which will be graded. After that, in the exam week there is a written exam which will be similar to the take-home exam. So far, the course has been quite intensive.

Such a long blog haha. I guess that’s it for now (felt good to rant about IC design:P). Oh one more thing; yesterday I had a shadow day. This means that a student joined me for my classes. That was my first time; think it went well:) If you think CE is something for you, but you are not sure, feel free to sign-up for a shadow day:)

Well, that’s it! Till next blog:)

Blog 6: Exams, Project, Results (and a new Quarter)

Heya,

I’m back after an eventful period of 4 weeks. Lots of things have taken place, so let me get on with it.

Firstly, I had the preparations for the exams and the exams themselves. I spend quite a lot of time going through all the material and trying to remember it all. I started with my oral exam for Methods and Systems for Algorithm Design. I was quite worried for this one; I don’t like to do oral exams (I’m more comfortable with written exams) and there was one chapter that I didn’t fully unerstand. Nevertheless, I was, in my opinion, well-prepared, and as long as I stayed calm there shouldn’t be a problem. Before the actual exam, I had 45 minutes to prepare myself for one of the chapters; ofcourse I got the topic I only understood that morning:P Luckily, I at least understood¬†the topic (for the ones interested: Retiming, which is basically a method to move registers in combinational circuits in order to improve the performance, area usage and/or power dissipation of the circuit), and the preparation went quite well. Eventhough I was able to go over all the material in that 45 minutes, I was still quite nervous. Me being nervous caused me to not answer the questions as good as I hoped, but it still went reasonably well. The paper presentation went pretty well, since I knew and understood all of the contents. The lab wasn’t so much touched upon, but the professors saw I had invested time in it, and told me it was sufficient. After waiting for 3 minutes, they called me back in the room and told me I got an 8 and that the lab was finished. I was so happy with that:) One down, two more to go I thought:)

Example of retiming (clock frequency is doubled by retiming the top circuit (source: http://1.bp.blogspot.com/-LDd–P6dGm4/TfDag9qsqII/AAAAAAAAABU/wfkACvvt4UI/s640/Retiming.png)

Three days later, that Friday, I had another exam: Performance Analysis. I think I still prepared myself quite well, although I went over all the horrible mathematical equations in the book without really remembering (and sometimes understanding) them. The day before the exam I practiced with the available practice exams, which went quite well, so I was quite confident. The exam itself took place at 9:00, which is quite early compared to the days before where I could sleep late(r):P I read the exam questions and I was happy. Except a really tough question 1, the questions were quite doable. It took me longer than expected though; I finished after 2 hours and 40 minutes, where I thought 2 hours would be enough. Afterwards, I discussed the exam with some friends, and we came to the consensus that it was definitely doable and passable. I got my result last week (I also looked at the answer last week): a 7.5:) I have to admit, after the initial happiness of passing the course, I was a bit disappointed; I think at least an 8 should have been doable, although a 7.5 is rounded up to an 8:) I don’t think I will do the re-exam for this course, unless my next exam period is relaxed haha! Anyway, two down and one more to go.

5 days later, on Wednesday, I had my last exam: Digital IC Design. I went over all the slides, I looked a bit in my book and printed (quite a lot of) useful slides. The day before the exam, I practiced with 5 practice exams, which all went reasonably well. What I noticed was that most of the time, the answers should be brief rather than long. I wish I would have taken this with me in the exam; during the exam I took a bit too much time for the questions I should have been able to answer brief and fast. On top of that, I was really confused at one question on which I spent at least 45 minutes, untill the assistants corrected an error in the question on the blackboard; the question now made sense to me, unfortunately I had spent so much time already :'(. During the whole exam, I felt the clock ticking, and I saw that I would end up in need for time. The last half hour I managed to answer 3 questions, albeit not to the best of my abilities. I don’t have the result yet; I can only hope to have an acceptable grade (really no idea if a 6 would be possible; let’s hope:)).

Last week, between the exam period of Q2 and the start of Q3, there was a week without any lectures –> Holidays! However, in my case I would call it normal week without lectures, or similarly, Project week. Why?! you might ask yourself; I have spent 4 out of the 5 days at the campus, together with my colleague, to work on the IC design project. The other day, I went to the dentist for a root canal treatment (which really wasn’t fun either;)). We had postponed all the project work until after the exams, so it really was needed. We first finalized the design of our TDC, before we went on with creating the remainder of the cells. At the moment we have a working architecture for the TDC with a resolution of 5 ps (which we are really happy with). Unfortunately, due to some (design) drawbacks, which took us quite some hours to fix, our design is a lot bigger in terms of area than expected. We have some things planned for this week (deadline of the final report is this Friday, the 12th of February): first assemble the whole TDC, including the counter, multiplexers and encoders, then simulate and simulate (and simulate and …) until we have what we need and finally we will finish writing the final report. We still haven’t given up yet on doing the layout, but it seems rather grim, seeing that we have only 4 days to go with quite some work to do.

For the ones interested in our TDC design: I won’t give all the details, but I can say that it is based on a ring oscillator augmented with a counter (for decreasing the amount of buffers/inverters in the ring oscillator). Since the resolution of just a ring oscillator will not go much lower than 20 ps, my colleague and I have designed a mechanism to enable a resolution of 5 ps (albeit at a large area cost:().

Example of a ring oscillator. The timing diagram shows that each subsequent output is delayed. This can be used in a TDC to measure the time between two pulses, by letting one pulse propagate in the ring oscillator (and counting through how many stages, or inverters, the pulse has propagated), until the second pulse goes up too. The amount of stages the signal has propagated through times the delay of one stage is the total measured time. Source: https://www.researchgate.net/profile/Dominique_Gibert/publication/280786005/figure/fig3/Figure-6-Simple-ring-oscillator-and-its-timing-diagram-T-pHLn-and-T-pLHn-denote.png

Q2 has almost finished, finally I must say;) However, Q3 has already started as of today. But I’ll tell you about Q3 in my next blog. You can expect it to be here before the start of March;) For now, I’m off to finish my project:P Cheers!:D

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