Posted in 2016

Blog 11: Finishing up Year 1 and looking forward


the past weeks have, again, been quite busy and stressful, but I managed at least;)

We have finished the Processor Design Project course, although we haven’t received a grade yet, so it’s to be decided if we are done after all;) The deadline of the report/design was last Monday (June 13th), so that Sunday we spent the whole afternoon and night on finishing up our design and to make our report. Unfortunately, we were not able to implement the 2-way associative cache. It seems that the memory structure that was implemented was optimized for Direct Mapped, so if we are to get the 2-way associative cache to work, we should look at the memory structure as well (instead of just looking at how the entries are stored). Luckily we achieved other improvements: bigger cache and better DDR to cache mapping and a Radix-4 multiplier and divider that need 16 instead of 32 cycles to get the result. The overall result is an increase in performance of almost 62.5% with negligible power increase (0.001 W); the area increase is significant unfortunately. Increasing block size (instead of retrieving 32 bits from the DDR at once we retrieve 64 bits) seemed to work except on one benchmark. The results of our improved processor in comparison with the baseline are shown below. 2 days after the deadline we had a symposium in which we showed our design and the results. The conclusion we took home was that we should have done a proper benchmark analysis. If we had done that, we probably wouldn’t have tried (and failed;)) to implement a branch predictor.

Improved processor vs baseline on needed execution cycles, area and power usage (Click for a better view; note: Y-axis is performance, meaning 1.x is better and 0.x is worse)

Improved processor vs baseline on needed execution cycles, area and power usage (Click for a better view; note: Y-axis is performance, meaning 1.x is better and 0.x is worse)

After PDP (temporarily) finished, I’ve been focusing on Quantum. Before this, however, I finished labs 3, 4 and 5. Labs 4 and 5 went pretty well, so I expect good grades;) As I was saying, last week till today I have been focusing on the Final Lab of this course (there is no exam). It consisted of 5 assignments (related to quantum circuits), of which assignment 3 was the hardest. Last week I finished all assignments except 3; it took me quite some time however. The assignments were definitely harder than the previous 2 labs, however this only meant I had to spend more time on them. I’m pretty sure I did quite well on these 4. One assignment was working on the Ninja Star circuit which can be seen below.

Example of a Surface Code circuit. If there is no error (0 instead of 1 for example) in any of the data qubits (D1-D9), no ancilla qubit (X/Z1-X/Z4). But let's say there is a bit-flip error in D3. This means that ancilla Z3 fires and becomes 1 (Z ancilla's fire when there is a X/bit-flip error).

Example of a Surface Code circuit. If there is no error (0 instead of 1 for example) in any of the data qubits (D1-D9), no ancilla qubit (X/Z1-X/Z4) will fire. But let’s say there is a bit-flip error in D3. This means that ancilla Z2 fires and becomes 1 (Z ancilla’s fire when there is a X/bit-flip error).

The 3rd assignment was about Grover’s algorithm, which is quite ingenious. It would take me some time to explain it, so instead I give you a link for the interested people;) I will say this, however: this algorithm is a good example of why Quantum Computing shows promise.

System Engineering:( Last Friday the symposium was held. I have to admit that it was pretty interesting to see what the other groups have worked on (2 minute pitch per group only;)) and to look at other groups’ posters. We also had to defend our own poster, which wasn’t that bad. Anyway, the course is finished now:) All that is left is to wait for the grade, hopefully I will get it soon!

So what’s next? Coming Tuesday is my (voluntary!) retake for Computer Arithmetic; let’s see if I can improve my grade. I only got a 6 on the exam, while I got a 8.something on the take home exam. I will also have to start on the VLSI SoC project with my partner. Probably we will do that next week after the retake. Somewhere these 2 weeks I will also meet with my internship supervisor, so that he can sign my application form. Then I can hand in this application form and just wait for approval:)

Oh, I forgot one thing. The past weeks I’ve also been talking with Dr. R. van Leuken of the Circuits and Systems group (CAS) here at the TU. He signed my Individual Exam Programme (basically your list of courses), so I will most likely (99%) do my Master Thesis with him as supervisor, next year when I get back from my internship in Germany. I advice you all to arrange these things a little bit earlier;) It takes more time than you image to arrange an internship and your Master Thesis:(

One more thing: Holiday:) I got my visa without further problems, so next Friday (July 1st) I will embark on the plane to China:D I’m thrilled to go; I’m less thrilled to pack:P Most likely I will also work on VLSI SoC in China and work on my Chinese, but the main focus will be holiday;)

I’m not sure when my next blog will be, it might be somewhere in the holidays, otherwise it will be when I get back (either from China or internship). I hope you at least enjoyed my blogs a bit, but most of all that they were helpful. Hell, maybe I convinced some of you to join me next year in CE šŸ™‚

That’s it for me for now. Good luck finishing this school year, and have an amazing holiday. Hope to see some of you in Delft next year:P

Blog 10: Mid-way Q4

Hi y’all,

it has been over a month since my last blog, which is a bit too much. I almost forgot to post today as well:(

The past month has been quite busy at timesļ¼Œ but at times it has been pretty relaxed as well. Quite some things have happened since the last time, so let me start.

I’ve had the milestone meeting for Processor Design Project. After a few days of hard working we finalized the changes to the cache. By just changing the cache size and mapping, we already achieved a small performance increase. But of course that’s not enough. The last 2 weeks I’ve been working, again, on the cache; I’m trying to change the mapping from direct mapped to 2-way associative cache. I’ve been unlucky so far, meaning I have some work to do coming two weeks. The deadline is nearing as well:(

Direct Mapped vs 2-Way Associative

Left: Direct Mapped, each main memory entry can only be stored in one cache entry.
Right: 2-Way Associative, each main memory entry can be stored in two cache entries.
So, in Direct Mapped if the cache entry is already occupied, the entry is discarded and replaced by the new entry. In 2-Way Associative, an entry is only replaced if both of the entries are occupied; so if only 2 main memory entries are competing for the same spot they are both stored.

The Quantum course has been really busy. Besides the usual following lectures, we have had labs. The first 2 labs were not really related to quantum; we had to model amplifiers (lab 1) and an amplifier plus Analog to Digital Converter (lab 2) in Matlab. These labs were more difficult than expected, and I’ve put a lot of work in them. The third lab is a bit more related; first a ‘normal’ silicon transistor has to be modeled and analyzed and after that the same has to be done for a silicon-germanium transistor (which is believed to be a possible solution in Quantum mechanics). This all had to be done in a simulator called COMSOL. The deadline for this is coming Monday. The fourth lab is very much related to Quantum; using a quantum simulator written by a PhD student we have to model not only quantum gates, but also slightly bigger circuits (for example a 2 bit counter). The deadline for this lab is coming Friday, and I’m well on my way to finish it. The course so far has been quite interesting, but also rather difficult. I don’t regret taking this course (yet) though, eventhough most of my time goes to this course.


Modeling a Silicon MOSFET transistor in the COMSOL simulator (Click the picture for a bigger one).

I don’t want to talk too much about System Engineering, but the report is hopefully almost finished. We had weekly meetings in which we divided the work, and then we just did the work. Every Friday one of us gave a presentation to the other groups and the supervisor (this week it’s my turn:P), and then we would get feedback on our report. Together with Q3 we/I put a lot more hours in this course than the 3 ECTS warranties unfortunately.

About the VLSI course nothing much is there to be said. So far I’ve just been attending the lectures. Coming Friday he will go into details about the 3 projects, and I’ll have to choose one together with my partner. It is still my plan to work on it before the holiday starts, but I’m not sure if I’m able to follow that plan:P

I’ve not only been busy with the courses. I’ve actually been quite busy getting an internship. And you know what? I succeeded:)!! At the end of August I’m going to Munich for an internship at Huawei for 10 weeks. I’m really excited, and nervous, about it. I already know the project I’m going to work on but not the details. I’m going to work on Lightfield Display design for Virtual Reality.

For those of who you don’t know what Light Field is, let me explain it in short. Light Field is all lightrays in each point in space moving in each direction; in other words it’s 4D, x and y direction and theta and phi angles. Currently this phenomenon is used in so called LightField Cameras. You know that when you’re taking a picture you have to focus your camera (so either what’s close to you is sharp or what’s far away)? With LightField Cameras this is not the case. You just take the picture, and afterwards, with software, you can change the focus over and over. This is possible because all the information is stored in the Light Field.

Example Light Field Camera

Example of a Light Field Camera. As can be seen, each of the balls, no matter their distance, has the same focus.

But that’s for cameras. My project is related to VR. This is because recently it has been discovered that Light Field can improve VR. Currently, using VR might make you nauseous. This has to do with your eyes not being able to change focus since every image is displayed (on a display) on the same short distance to your eyes. You can already guess, Light Field might be able to solve this problem, by constantly changing the focus, mimicking the reality better. I didn’t know anything about Light Fields before I got this internship, but now I’m really interested. I almost can’t wait to start:) (of course, I want to enjoy my holiday first!)

Talking about the holidays, I’ve already booked my tickets:) From July 1st/2nd till August 22nd I’ll be in lovely China. At least, that’s the plan, but I don’t have a visa yet. 2 weeks ago I went to apply for it, but they didn’t accept it, and they told me I can’t spend so much time in China without leaving in between. So 1 week ago I went again, this time with my Chinese girlfriend. After 10 minutes of Chinese talk they solved the problem and suddenly I might be able to stay this long. Lesson learned: bring a Chinese person if you want to apply for a Chinese visa. Although it also helped that the second time the lady could speak Dutch:P Coming Thursday I’m going there again to pick up my visa; let’s hope they don’t call me before then saying there is a problem;)

Well, that’s it for now. Maybe it seems like I haven’t been all too busy the past month, but let me assure you: I have been quite busy the past month;) Luckily, having only lectures on 2 days helps a lot with that:P I really hope I won’t forget to write my next blog; I’ll try to be faster than this time as well:P

Till next time, cheers:)!

Oh, and it looks like summer is coming back slowly. Don’t forget to enjoy it while it lasts;)!

Blog 9: Starting Q4 and LoL


it took me a bit longer than expected to write this blog, but c’est la vie I guess. At least things have happened since my last blog:)

I have worked hard on my practice exam for Computer Arithmetic. I think I’ve spent at least 10 hours on it. This was mostly because I had to get familiar with the material and look at some examples. Honestly, I have spent the whole week before the exam, minus 2 days, on this practice exam, so I was a bit nervous for the exam; the exam is only 3 hours. The last two days I focused on other material in case that would be in the final exam. The exam itself was okay-ish. Unfortunately I didn’t manage my time well and as a result I couldn’t finish 1.5 out of 9 questions. Nonetheless, I thought it went pretty okay; today I got the confirmation: I have a 7:) I’m not quite sure if that’s only my final exam, or my take-home exame, or both, but whatever! I’m actually a bit disappointed; I hoped for an 8.

I have also uploaded my final essay for Network Security. I’m glad it’s finished, I’ve put a lot of effort in it. I also finished the third and last exercise sheet, which was posted the day of the NXP trip. It consisted of only two questions and an optional programming part. I’ve chosen to not do the programming part due to my oral exam of VLSI TTR on Monday (i.e., today; deadline of the sheet was Sunday, i.e., yesterday). The questions were not hard, so that should be fine. I’m still waiting for my essay- and final grade. I think I will pass this course, but I want to know for sure;)

Friday the 15th of April we went to NXP in Nijmegen for the VLSI TTR course. It was quite interesting; a few lectures were given and I’ve seen quite a lot of different test machines (seeing the machines was quite impressive). There are possibilities for an internship or master thesis at NXP, which is pretty cool:) Besides the visit, I also need to finish the course; that’s exactly what I’ve done today. I took the oral exam together with my two colleagues with which I’ve done the assignments. The exam took about 2 hours:( Honestly, it could’ve went a lot better, but it turns out I did well enough to get an 8:D Thus I’ve passed this course:)

The exam for Systems Engineering didn’t go as planned unfortunately. I’m still being hopeful, but I’ll have to wait. It was only 3 questions (with each 3 sub-questions), but it consisted of a lot of reading work (which I had anticipated). I can honestly say that my writing hand was super tired after the exam:P

This quarter I decided to follow three courses besides Systems Engineering: Processor Design Project (track course, so not really a choice;)), VLSI System on Chip and Electronics for Quantum Computation (both specialization courses). VLSI SoC is basically for extra credits, since I’m planning to do an internship of 15 points (initially I planned to follow courses for 11 ECTS next year); without this 4 ECTC, I already have enough non-thesis credits.

Processor Design Project is quite interesting. There was one kick-off lecture, and there will be an intermediate meeting to see if we are on the right track, but for the rest there is nothing planned. We are given a processor design written in VHDL, and we have to make it faster in groups of three. This course follows Computer Arithmetic, so surely there are arithmetic optimizations to be done, but you can also think of architectural optimizations. I already have a group, and for coming Wednesday I will look at the source code and the course description, so that we can discuss it on Thursday.

VLSI SoC seems like a really interesting course, hence why I’m taking it for extra credits. For now, lectures are given (though not in the coming two weeks), but after that you have to design a System on Chip in groups of 2 (or 1). The deadline is very lenient; if you want you can send it in the summer, or even next year. I’m going to work together with Reynaldi again (same partner as Digital IC Design), and obviously we are trying to finish it before the summer. I will elaborate more on the project in one of my next blogs!

The quantum course is looking to be quite intensive and complex. I think it will be interesting though. The main reason I’ve chosen this course is because of the Quantum part, which is a trending and upcoming part of Computer Engineering. Did you know Intel invested 50 Million Dollar in TU Delft to design a working Quantum Computer? So yeah, Quantum Computing is quite big at the moment, so I thought it would be interesting to follow is course (unfortunately I didn’t follow introduction to Quantum Computing in Q1). For this course, there will be lecutres and lab assignments. The first lab assignment is due coming Friday and it looks quite complicated:O.

My schedule of this quarter is pretty empty. Tuesday I have 2 lectures and Friday I have 3; the rest of the days I have nothing scheduled. But surely project meetings will be scheduled on these days:( This quarter is looking quite interesting, so I am looking forward to it. However, it’s also looking intensive and I almost can’t wait for the summer holiday:(

As mentioned in my last blog, LCS (League of Legends Championship Series) Europe Finals came to Ahoy in Rotterdam. Together with a lot of people of the E-sports club in Delft (DSEA) I went to this event as a volunteer. It was really amazing and I’ve had a blast. Saturday I applied (not-so) temporary tattoos on peoples arms, and sometimes faces, and on Sunday I took pictures of the crowd with famous youtuber Sp4zie (you can probably see me in his latest vid). After the tattoos I watched the 3rd place match (see picture) which was awesome eventhough the team I was rooting for lost, and after taking pictures I watched the finals which was even more amazing, also beacause the team I was rooting for won. This was my first E-sports/LoL event, and I certainly hope it’s not my last. After the games, I took pictues of the crowd with the players and shoutcasters. A bonus: afterwards I also took pictures with the teams and casters (4 times haha). I also met and talked with a retired German player (CandyPanda) who was behind me in the line for ice cream, and I talked with the owner of the winning team. All in all, it was amazing and to all of you LoL fans: next time it comes to Rotterdam, you should go there; I know I will:)

Inside Ahoy. On screen the casters, on stage the players. That's a lot of people:)!

Inside Ahoy. On screen the casters, on stage the players. That’s a lot of people:)!

On the photo with Fnatic:)!

On the photo with Fnatic:)!

I have busy weeks coming up. I hope I will have the time to write another blog (again, shorter interval than between this blog and the last).


Small edit: I’ve mentioned that I want to do an intership first quarter of next year. In my next blog, when I hopefully have more information, I will elaborate on this!

Blog 8: I’m still alive;) Finalizing Q3

Hi y’all,

a long time has past since my last blog. Frankly, I haven’t done much else than following my courses (which took me enough time), but I thought it would be time for my next blog;)
I got back the two missing results from Q2, Profile Orientation (writing the essay) and Digital IC Design. I got a High Pass for the essay, meaning that it was better than average, yeey:D For IC Design, I got a 7.5, so I’ve passed it at least! I’m not quite sure what the separate grades (project and exam), but I’m pretty sure the exam is not that high. Therefore I have (almost) decided to retake the exam at the end of this quarter. Regardless, I have gotten all my points for the first 2 quarters, which is pretty awesome:)

Let me give you an update on my courses. First up, Computer Arithmetic. 4 homework assignments have been posted, including their answers. Honestly, I haven’t put much effort into these homework assignments, since the other courses were quite intensive. I have, however, followed all the lectures (minus 1 where I was late due to NS and half the lecture gone to waste because of a fire alarm going of wrongly:P). The exam is next week Wednesday, which I’ll naturally attend. Before the exam, there is a take-home exam due on the day of the exam. It’s basically a practice exam, but it is part of the final grade (40ish%). I have went over the lecture slides, and I will start today with the take-home exam. I’m confident I can make something out of it:)

Then Network Security. At the time of writing my last blog it was merely following lectures. Since then, I have done a lab assignment (which didn’t go as well as planned) on the Spanning Tree Protocol (STP) in switches, and 2 exercise sheets. These exercise sheets consisted of `simply’ answering questions about the material covered in class (with the help of google;)). However, part of the 2nd exercise sheet was practical stuff. We had to write a program capable of 2 things: ARP spoof someone and overflow the CAM table of a router.

ARP spoofing in a nutshell is intercepting someone’s ARP request (PC asks which PC, with which MAC address, has this IP address) and acting like his target. This is done by sending an ARP reply (IP address X is at this PC with MAC address y) to the victim saying that you are the victim’s target (but you are not;)). Everytime the victim sends messages to his intended target, you are getting these messages. See the picture below:

ARP spoofing visualized. The attacker sits between two PCs. When Greend sends a message to Blue, the attacker intercepts (and thus can read) it and forwards it to Blue.

ARP spoofing visualized. The attacker sits between two PCs. When Greend sends a message to Blue, the attacker intercepts (and thus can read) it and forwards it to Blue (source: google).

Every router has a CAM table, which is used for forwarding packets. In a CAM table overflow attack, you are sending a lot of messages with as source different MAC- and IP addresses with as goal that the CAM table cannot store it anymore, effectively making the router into a hub (forwarding each and every message to all of its ports). In the picture below, a succesfull CAM table overflow attack can be seen:

Succesful CAM table overflow attack. Hub-like behaviour can be seen; packets with various source- and destination IP addresses are captured, including packets that are not coming from or are directed to the host computer.

Succesful CAM table overflow attack. Hub-like behaviour can be seen; packets with various source- and destination IP addresses are captured, including packets that are not coming from or are directed to the host computer (source: google).

I have written a program in Java (with the help of the pcap4j library) that can do both. It was not as easy to test, so I’m not sure I did it correctly, but I’m positive;) Eventhough it cost me quite some time to write the program, I have had quite some fun and I have learned a lot:) I’ve also been working on my essay. I have a draft version of just over 7 pages, which I still have to alter slightly (spelling errors etc.). The deadline is tomorrow, so I’ll finish this tomorrow. I have put a lot of work in my essay, and I feel quite good about it. It counts for 65% of the grade, so it better be a good grade;) A 3rd exercise sheet might follow, but after that I’m done with this course (there is no exam).

There are no more lectures for the VLSI test course. Besides the lectures, I have finished 3 homework- and 2 lab assignments together with 2 friends. The Friday after my exam there will be a visit to NXP, which I’m looking forward to. There will also be an oral exam, but I think that will be after the visit, so somewhere in Q4.

And lastly, Systems Engineering. The lectures have finally finished and I’m in a group of 11 people for the project next quarter. I have chosen for the project: a smart DC home (which I’ve done for my bachelor thesis as well). I’m in the group with 2 friends, so that’s nice;) We have including me and my friend three Computer Engineers which might be a bit too much:P We have held a few meetings to start with the project, and Monday we have submitted our first report. I think we worked quite efficiently, so I’m pretty confident that we will do well next quarter;) The week after the Computer Arithmetic exam, also on Wednesday, I have the exam for Systems Engineering. The day after, I have the Digital IC Design exam. I don’t think there is too much material for the exam, but it will probably be hard. I hope to spend 1 day on IC design, before studying the System Engineering exam; should be fine!

If I were to summarize this quarter, I’d say the beginning was quite relaxing (except the IC design stress:O). Unfortunately, most of the workload came in the second half of the quarter (because of IC design extending to the beginning of Q3 this was actually a good thing); VLSI labs, Network Security exercise sheets and Systems Engineering Project. However, I have had quite some free time here and there (especially the week after IC design), so I’m quite satisfied with this quarter. I’m really happy with the three courses I’ve chosen (let’s forget System Engineering); each of them was quite interesting and I’ve learned a lot. Computer Arithmetic was boring at times I should mention though, but it’s a prerequisite for the Processor Design project in Q4.

This week I will work hard on Computer Arithmetic; I will have to finish the take-home exam. The upside is that it should be good practice for the final exam;) After the exam, I will focus on System Engineering and hopefully 1 day for IC design. The IC design retake is just a bonus for me; I hope to improve my grade, but System Engineering is the main focus for that week! After the two exams, I have the visit to NXP which I’m looking forward too. But I’m most excited for the weekend after: together with a group of around 20 people, I will go to Rotterdam for the League of Legends LCS tournament:D It will be my first time visiting a LoL event, so I’m obviously thrilled:)

I will write about my exams, the NXP visit and the LoL tournament in my next blog. I hope the wait will be shorter than for this blog:(

See you next time:)

Blog 7: Getting back my life and start of Q3

Hi y’all,

the last 3 weeks have been the hardest ones of this year. Most of it, I have been finishing up on the project (two times extended deadline) while at the same time following lectures.

Let me first get Digital IC Design over with. If I think back to it, I’m still amazed we managed to finish it. Two weeks ago, in the final week before the deadline, we still had quite some stuff to do. Combining all the pieces didn’t take so much time, but sizing all the transistors, to get exact timing results took a lot more time than anticipated. Needless to say, we were happy with the week extension that was announced one(!) day before the initial deadline. At this point, all we had for the report was an introduction, so yeah. Anyway, after this joyful news, we took it a bit more relaxed for two days before going back to hardcore IC design. We oversaw many small things, which resulted in us (mainly my colleague though) having to size the transistors over and over again, which might not be hard, but it takes a lot of time and is so tedious. Moreover, we didn’t know that each component needed a pin for Vdd and Ground, so I spent a lot of time altering all the components of our system. At this point we are already in the last week, and it’s quite clear to us that there will be no time for the layout. Up untill the day before the deadline, we are trying to get our TDC to work with the provided testbench; this was (un)surprisingly harder than expected. We finally got it to work, and were planning to spend the last day on simulations and the report. And then: another extension untill the Monday. At this point, we just wanted it to be finished, we already put so much time on this project:( When we left Friday (later than 8 pm!) something still didn’t work completely. My colleague fixed it over the weekend, and Monday we ran simulations and wrote the report. On Tuesday, we showed the working of our design to the TAs, who told us that not many groups showed their designs up untill then. The TAs were pretty lenient and they saw our 5 ps resolution (yay:D).

Eventhough we have spent so much time on the project, and that we had countless of days where we stayed till 8 pm, I do not regret taking this course. I have learned a lot, and at times the project was actually fun:) I do think that the project was a bit too complicated, and that not everything was communicated clearly (Vdd pins anyone:P?). I also think that, because we were still working on this project 3 weeks into Q3, the project messes with the courses of Q3, which is not preferable. Next Monday and Tuesday there will be symposiums in which every group will present their TDC design. My presentation will be Tuesday, however I need to be there Monday as well. I’ll let you know how it went:)

Three weeks have already passed of quarter 3:O This quarter, I have decided to follow Computer Arithmetic (Track course), VLSI Test Technology and Reliability and Network Security (Specialization courses). I actually wanted to take Operating Systems as homologation (bachelor) course, but the exam conflicted with my compulsory common core course System Engineering. Jup, 4 courses again this quarter:P

System Engineering is about multi-discplinary design of systems. It is about high-level design and integration of blocks, of which you don’t necessarily need to know the complete functioning. I have two lectures (both starting 8:45:(); on Thursday a guest lecture is given that shows the place of System Engineering in the industry and on Friday a theory lecture is given in which the steps in System Engineering will be explained. This will be needed for next quarter; then we will work in groups of 11 students from different programs. In this project, we will have to design a system following some steps of System Engineering. Frankly, I don’t like the Thursday lectures, and I’m not thrilled for the project; the Friday lectures are okay. At the end of this quarter I will have an exam based on (mostly) the Friday lectures.

VLSI TT&R is about the testing of a chip. Did you know that functional testing of an 129 input and 65 output adder takes 2.15 x 10^22 years (source: Prof. S. Hamdioui)? Well, neither did I;) This course is all about making chips testable; how can chips be tested in a fast way, without costing too much while catching all the bad chips? Besides the theory, links are made with the industry. It’s a really interesting course, and so far I’m glad I took it. Prof. Hamdioui is very enthusiastic too, which helps a lot in liking the course:P There is no written exam for this course. There are three labs (groups of three), which consists of first applying the theory to test circuits and secondly of applying the theory on test circuits in software. At the end of this quarter there will be an oral exam, in which three students will have to design a test for a given circuit.

Network Security is quite an interesting course as well. The professor will, over the course of this quarter, go over all layers of the OSI model (including things as Wifi and tapping ethernet cables) and will show us why all consisting protocols are unsafe. He also requested us to send him encrypted (pgp) emails:P So far, the course has been quite intensive, but as I said quite interesting as well. There will be no written exam for this course. During the quarter, exercise sheets will be given that will account for 35% of the grade. Besides that, an essay (or a software/hardware project) has to written. The topic I have gotten is methods of Threat Analysis (such as Attack Trees, see below). I have started already, and almost finished the first (Attack Trees) out of three methods.

Famous Attack Tree example of Schneier. The top node is the goal of the attacker; the nodes below that are actions to achieve the goal. Source:

There is not much to say about Computer Arithmetic yet honestly. Until now it has just been following lectures and practicing with a homework assignment. These assignments are optional and will be explained in class. There will be practice take-home exam, which will be graded. After that, in the exam week there is a written exam which will be similar to the take-home exam. So far, the course has been quite intensive.

Such a long blog haha. I guess that’s it for now (felt good to rant about IC design:P). Oh one more thing; yesterday I had a shadow day. This means that a student joined me for my classes. That was my first time; think it went well:) If you think CE is something for you, but you are not sure, feel free to sign-up for a shadow day:)

Well, that’s it! Till next blog:)

Blog 6: Exams, Project, Results (and a new Quarter)


I’m back after an eventful period of 4 weeks. Lots of things have taken place, so let me get on with it.

Firstly, I had the preparations for the exams and the exams themselves. I spend quite a lot of time going through all the material and trying to remember it all. I started with my oral exam for Methods and Systems for Algorithm Design. I was quite worried for this one; I don’t like to do oral exams (I’m more comfortable with written exams) and there was one chapter that I didn’t fully unerstand. Nevertheless, I was, in my opinion, well-prepared, and as long as I stayed calm there shouldn’t be a problem. Before the actual exam, I had 45 minutes to prepare myself for one of the chapters; ofcourse I got the topic I only understood that morning:P Luckily, I at least understoodĀ the topic (for the ones interested: Retiming, which is basically a method to move registers in combinational circuits in order to improve the performance, area usage and/or power dissipation of the circuit), and the preparation went quite well. Eventhough I was able to go over all the material in that 45 minutes, I was still quite nervous. Me being nervous caused me to not answer the questions as good as I hoped, but it still went reasonably well. The paper presentation went pretty well, since I knew and understood all of the contents. The lab wasn’t so much touched upon, but the professors saw I had invested time in it, and told me it was sufficient. After waiting for 3 minutes, they called me back in the room and told me I got an 8 and that the lab was finished. I was so happy with that:) One down, two more to go I thought:)

Example of retiming (clock frequency is doubled by retiming the top circuit (source:–P6dGm4/TfDag9qsqII/AAAAAAAAABU/wfkACvvt4UI/s640/Retiming.png)

Three days later, that Friday, I had another exam: Performance Analysis. I think I still prepared myself quite well, although I went over all the horrible mathematical equations in the book without really remembering (and sometimes understanding) them. The day before the exam I practiced with the available practice exams, which went quite well, so I was quite confident. The exam itself took place at 9:00, which is quite early compared to the days before where I could sleep late(r):P I read the exam questions and I was happy. Except a really tough question 1, the questions were quite doable. It took me longer than expected though; I finished after 2 hours and 40 minutes, where I thought 2 hours would be enough. Afterwards, I discussed the exam with some friends, and we came to the consensus that it was definitely doable and passable. I got my result last week (I also looked at the answer last week): a 7.5:) I have to admit, after the initial happiness of passing the course, I was a bit disappointed; I think at least an 8 should have been doable, although a 7.5 is rounded up to an 8:) I don’t think I will do the re-exam for this course, unless my next exam period is relaxed haha! Anyway, two down and one more to go.

5 days later, on Wednesday, I had my last exam: Digital IC Design. I went over all the slides, I looked a bit in my book and printed (quite a lot of) useful slides. The day before the exam, I practiced with 5 practice exams, which all went reasonably well. What I noticed was that most of the time, the answers should be brief rather than long. I wish I would have taken this with me in the exam; during the exam I took a bit too much time for the questions I should have been able to answer brief and fast. On top of that, I was really confused at one question on which I spent at least 45 minutes, untill the assistants corrected an error in the question on the blackboard; the question now made sense to me, unfortunately I had spent so much time already :'(. During the whole exam, I felt the clock ticking, and I saw that I would end up in need for time. The last half hour I managed to answer 3 questions, albeit not to the best of my abilities. I don’t have the result yet; I can only hope to have an acceptable grade (really no idea if a 6 would be possible; let’s hope:)).

Last week, between the exam period of Q2 and the start of Q3, there was a week without any lectures –> Holidays! However, in my case I would call it normal week without lectures, or similarly, Project week. Why?! you might ask yourself; I have spent 4 out of the 5 days at the campus, together with my colleague, to work on the IC design project. The other day, I went to the dentist for a root canal treatment (which really wasn’t fun either;)). We had postponed all the project work until after the exams, so it really was needed. We first finalized the design of our TDC, before we went on with creating the remainder of the cells. At the moment we have a working architecture for the TDC with a resolution of 5 ps (which we are really happy with). Unfortunately, due to some (design) drawbacks, which took us quite some hours to fix, our design is a lot bigger in terms of area than expected. We have some things planned for this week (deadline of the final report is this Friday, the 12th of February): first assemble the whole TDC, including the counter, multiplexers and encoders, then simulate and simulate (and simulate and …) until we have what we need and finally we will finish writing the final report. We still haven’t given up yet on doing the layout, but it seems rather grim, seeing that we have only 4 days to go with quite some work to do.

For the ones interested in our TDC design: I won’t give all the details, but I can say that it is based on a ring oscillator augmented with a counter (for decreasing the amount of buffers/inverters in the ring oscillator). Since the resolution of just a ring oscillator will not go much lower than 20 ps, my colleague and I have designed a mechanism to enable a resolution of 5 ps (albeit at a large area cost:().

Example of a ring oscillator. The timing diagram shows that each subsequent output is delayed. This can be used in a TDC to measure the time between two pulses, by letting one pulse propagate in the ring oscillator (and counting through how many stages, or inverters, the pulse has propagated), until the second pulse goes up too. The amount of stages the signal has propagated through times the delay of one stage is the total measured time. Source:

Q2 has almost finished, finally I must say;) However, Q3 has already started as of today. But I’ll tell you about Q3 in my next blog. You can expect it to be here before the start of March;) For now, I’m off to finish my project:P Cheers!:D

Blog 5: Back to reality (and exams)

Hi y’all,

let me get the formitality out of the way;) I wish you all a very happy New Year and I hope all your wishes will come true. I hope to see some of you at the TU Delft at the end of this year, where you have just started your Master Computer Engineering (a man can dream:P). Anyways, the holidays have unfortunately ended and I’m back to reality. But before I talk about reality, let me talk about my holidays:D

Christmas was really nice; first Christmas day I had dinner with my father, brother, sisters and following, and on the second day I travelled all the way to Limburg (south-east of the Netherlands, known for Maastricht probably) to see my family. Ā New Year’s Eve wasn’t spectacular (however nor am I); I went to some friends and played an old Dutch game called “Sjoelen” (see the picture:)) and afterwards a friend came over and we played some games:) Oh, before that, I made the typical Dutch treat “Oliebollen”, which can be described as a ball of dough, with raisins, fried in oil. They were delicious haha. For the rest: I went to the (Charles) Dickens’ Fest in Deventer, I went ice skating in Rotterdam, I did karting and lasergaming in Den Haag.S490000-1-Sjoelbak-voor-senioren

(Old Dutch game “Sjoelen”. Get the stones in one of the 4 holes (2, 3, 4, 1 points respectively))


(Oliebollen (not the ones I made unfortunately:())

That was the fun stuff; as I’ve told you, university stuff needed to be done as well. On average, I spent 2 hours per day on that stuff (excluding Christmas and New Year). I am quite proud I was actually able to keep doing that for 2 weeks:P, and with the progress I’ve made. The whole first week I have spent on the Digital IC design project; at the end of the holidays we had all the cells except the delay element, although the counter wasn’t fully functional yet. I have also spent some time on the Systems Design lab; at the end of the holidays it wasn’t quite finished yet, but some progress has been made. One day I have spent on my essay; I read it through, and made some drastic changes and it is a bit better now:) I worked a bit on the Performance Analysis homework, however I didn’t finish it completely.

So far the holidays, so long my friend. I already have undergone another week of university stuff:P This past week my focus was primarily on the IC design project (which resulted in 4 days of at least 4 hours working in the lab room with my colleague), since the deadline of the midterm report was last Friday. We finished the design of the cells; we changed the counter design (old design couldn’t be asynchronously resetted) and we have decided to use an inverter as the delay element. Unfortunately, the design we had first chosen had a maximum possible resolution of around 16 ps (a TDC measures the time between 2 pulses, a start and a stop. The resolution is the smallest amount of time it can measure). This would fulfill the requirement of 30 ps, but according the the teacher, people from last years achieved resolutions of around 2 to 10 ps. Therefore we have worked on a second design which can achieve a resolution between 2 to 5 ps. This cost us a good 2 days. The rest of the time we have spent working on simulations and writing the midterm report. I am quite happy with our progress so far, however quite some work lies ahead still. The good thing, though, is that now I understand what our design will be, I am actually having some fun doing this project!:)

I have also spent some more time on de System Design lab. It is almost finised, however I’m having a weird result, which I have asked/mailed the teacher about. After that is resolved, all that there is left to do is to compile a report for the oral exam. I also finished the Performance Analysis homework (5th and 6 assignment), so I’m done with those homework assignments:D Lastly, last Friday I handed in my Essay. I reread it once more, and changed a few small things and then I handed it in. I’m hoping for at least a pass, possibly a high pass, meaning this part is finally finished:)

Coming week I have nothing planned, which means I can prepare for my exams. I have the oral exam for System Design on Tuesday the 19th of January,Ā the Performance Analysis Exam on Friday the 22nd of January andĀ the IC Design exam on Wednesday the 27th of January. The oral exam consists of 15 minutes answering questions about the material, 10 minutes of presenting an idea of a paper and 5 minutes discussing the lab.IĀ still have to prepare theĀ first 2 parts. For IC Design I already studied some material, but I still have to study it carefully. The same goes for Performance Analysis. A lot of studying to do the next 3 weeks;) Coming week I will focus mainly on System Design and a bit on Performance Analysis. Next week, after the Oral exam, I will focus on P.A.. The week after will be fully for IC Design. I still need to work on the IC Design project inbetween though.

That’s it for now, thanks for reading:) I hope to be back with my next blog the weekend after my exams. Wish me good luck:)! Cheers!

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